Definition

backside bus

In a personal computer with an Intel processor chipset that includes a Dual Independent Bus (DIB), the frontside bus is the data path and physical interface between the processor and the main memory (RAM). The backside bus is the data path and physical interface between the processor and the L1 and L2 memory. Both the frontside bus and the backside bus can be in use at the same time, meaning that the processor gets more done in a given number of pulses per second (see clock speed).

Prior to Intel's Pentium Pro processor, both the L2 cache and RAM were accessed using the same bus, creating an occasional bottleneck and reducing the overall throughput of the computer. Beginning with the Pentium Pro, the level-2 (L2) is packaged on the same module or chipset as the processor. Intel's Dual Independent Bus (DIB) design separates and coordinates accesses between the processor and RAM and accesses between the processor and the L2 cache. The frontside bus operates at 66 or 100 MHz, depending on the chipset. In the Pentium Pro, the backside bus (to the L2 cache) operates at the same clock speed as the processor. In the Pentium II, the backside bus operates at one-half the processor clock speed.

This was last updated in July 2007
Posted by: Margaret Rouse

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